A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power

• Published in: IEEE journal of solid-state circuits 2012-12, Vol.47 (12), p.2974-2988
• Main Authors: Marzin, Giovanni, Levantino, S., Samori, C., Lacaita, A. L.
• Format: Article
• Language: English
• Subjects: ADPLL; Applied sciences; Bandwidth; bang-bang; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); DCO; Dielectric, amorphous and glass solid devices; DPLL; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Frequency filters; Frequency modulation; frequency synthesis; lead-lag; Oscillators, resonators, synthetizers; Phase locked loops; Phase modulation; phase modulator; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; TDC; TDC-less; Tuning; two-point injection
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2012.2217854

This paper presents a low-power high-bit-rate phase modulator based on a digital PLL with single-bit TDC and two-point injection scheme. At high bit rates, this scheme requires a controlled oscillator with wide tuning range and becomes critically sensitive to the delay spread between the two injection paths, considerably degrading the achievable error-vector magnitude and causing significant spectral regrowth. A multi-capacitor-bank oscillator topology with an automatic background regulation of the gains of the banks and a digital adaptive filter for the delay-spread correction are introduced. The phase modulator fabricated in a 65-nm CMOS process synthesizes carriers in the 2.9-to-4.0-GHz range from a 40-MHz crystal reference and it is able to produce a phase change up to ±π with 10-bit resolution in a single reference cycle. Measured EVM at 3.6 GHz is -36 dB for a 10-Mb/s GMSK and a 20-Mb/s QPSK modulation. Power dissipation is 5 mW from a 1.2-V voltage supply, leading to a total energy consumption of 0.25 nJ/bit.