DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler

In the last decade, a considerable amount of effort was spent on raising the implementation level of hardware systems by automatically extracting the parallelism from input applications and using tools to generate Hardware/Software co-design solutions. However, the tools developed thus far either fo...

Full description

Saved in:
Bibliographic Details
Main Authors: Nane, R., Sima, V., Olivier, B., Meeuws, R., Yankova, Y., Bertels, K.
Format: Conference Proceeding
Language:English
Subjects:
C-to-VHDL
DWARV
Engines
FSM
Hardware
Hardware design languages
HW Compiler
IP networks
Kernel
Libraries
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In the last decade, a considerable amount of effort was spent on raising the implementation level of hardware systems by automatically extracting the parallelism from input applications and using tools to generate Hardware/Software co-design solutions. However, the tools developed thus far either focus on particular application domains or they impose severe restrictions on the input language. In this paper, we present the DWARV 2.0 compiler that accepts general C-code as input and generates synthesizable VHDL for unrestricted application domains. Dissimilar to previous hardware compilers, this implementation is based on CoSy compiler framework. This allowed us to build a highly modular compiler in which standard or custom optimizations can be easily integrated. Validation experiments showed speed-ups of up to 4.41× when comparing against another state of the art hardware compiler.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2012.6339221