SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration

Dynamic partial reconfiguration is a growing need for SRAM FPGA-based embedded systems. This feature allows reconfiguring parts of the FPGA while others continue to run. But it may introduce security breaches affecting FPGA configuration. In this paper, a secure protocol to ensure confidentiality, i...

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Bibliographic Details
Main Authors: Devic, F., Torres, L., Crenne, J., Badrignans, B., Benoit, P.
Format: Conference Proceeding
Language:English
Subjects:
Ash
Encryption
Field programmable gate arrays
Nonvolatile memory
Protocols
Random access memory
Online Access:Request full text
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Description
Summary:Dynamic partial reconfiguration is a growing need for SRAM FPGA-based embedded systems. This feature allows reconfiguring parts of the FPGA while others continue to run. But it may introduce security breaches affecting FPGA configuration. In this paper, a secure protocol to ensure confidentiality, integrity, authenticity and up-to-dateness is described and applied to dynamic partial reconfiguration. Two common threat models are addressed for industrially-driven use cases. The implementation can perform both secure update and reconfiguration without significantly affecting performances.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2012.6339241