Exploiting run-time reconfiguration in stencil computation

Stencil computation is computationally intensive and required by many applications. This paper proposes an approach to exploit run-time reconfigurability of field-programmable accelerators for stencil computation. System throughput is optimized by partitioning, analysing and scheduling tasks in appl...

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Bibliographic Details
Main Authors: Xinyu Niu, Qiwei Jin, Luk, W., Qiang Liu, Pell, O.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Analytical models
Field programmable gate arrays
Hardware
Kernel
Partitioning algorithms
Throughput
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Summary:Stencil computation is computationally intensive and required by many applications. This paper proposes an approach to exploit run-time reconfigurability of field-programmable accelerators for stencil computation. System throughput is optimized by partitioning, analysing and scheduling tasks in applications to remove idle functions. To evaluate the proposed approach, Reverse Time Migration (RTM), a high performance application, is developed. Our optimized runtime reconfigurable solution, which targets a Virtex-6 FPGA in a Maxeler MAX3424A system, can achieves an improved throughput of 102.8 GFlop/s, up to two orders of magnitude faster than the CPU reference designs, 1.59 times faster than the best published GPU and FPGA results, and 1.45 times faster than an optimized static implementation.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2012.6339257