Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC

As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previo...

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Bibliographic Details
Main Authors: Wei-Hao Hsiao, Yi-Ting He, Lin, M. P.-H, Rong-Guey Chang, Shuenn-Yuh Lee
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Accuracy
Capacitors
Layout
Manuals
Optimization
Routing
Systematics
Online Access:Request full text
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Description
Summary:As the precision of the capacitance ratios among binary-weighted capacitors is the key to accuracy/performance of charge-scaling digital-to-analog converters, it is very important to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous works only focused on common-centroid placement optimization with the consideration of random and systematic mismatch. This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on circuit accuracy/performance. Experimental results show that, compared with the manual layout, the layout generated by the presented approach can achieve even smaller layout area and better circuit accuracy/performance within much shorter time.
DOI:10.1109/SMACD.2012.6339445