A new high-performance VLSI architecture for generating 2-dimensional phase holographic pixels

In this paper we propose a new hardware architecture for high-speed to reduce the amount of hardware resource for CGH (computer generated hologram) calculation without sacrificing the performance. It uses the block-parallel method in calculating a CGH. After analyzing the CGH equation, we rearrange...

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Bibliographic Details
Main Authors: Yoon-Hyuk Lee, Young-Ho Seo, Jisang Yoo, Dong-Wook Kim, Hyun-Jun Choi
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Calculators
Computer architecture
computer generated hologram (CGH)
Field programmable gate arrays
FPGA
Fresnel
Hardware
hardware implementation
Indexes
Light sources
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Summary:In this paper we propose a new hardware architecture for high-speed to reduce the amount of hardware resource for CGH (computer generated hologram) calculation without sacrificing the performance. It uses the block-parallel method in calculating a CGH. After analyzing the CGH equation, we rearrange it to design hardware to fit to our purpose. The main block of the proposed hardware is common term calculator (CTC), index term calculator (ITC), and update term calculator (UTC) which compose a CGH processor that can calculate a flexible size of CGH sub-block.
DOI:10.1109/ISCIT.2012.6381019