A Three-Dimensional Integrated Accelerator

We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has bee...

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Main Authors: Mehdipour, F., Nunna, K. C., Inoue, K., Murakami, K. J.
Format: Conference Proceeding
Language:English
Subjects:
Arrays
Data flow graph
Delay
Pipelines
Reconfigurable data-path accelerator
Routing
Switches
Three-dimensional integration
Through-silicon via (TSV)
Through-silicon vias
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creator Mehdipour, F.
Nunna, K. C.
Inoue, K.
Murakami, K. J.
description We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.
doi_str_mv 10.1109/DSD.2012.15
format conference_proceeding
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Arrays
Data flow graph
Delay
Pipelines
Reconfigurable data-path accelerator
Routing
Switches
Three-dimensional integration
Through-silicon via (TSV)
Through-silicon vias
title A Three-Dimensional Integrated Accelerator
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