Automated Post-Silicon Debugging of Failing Speedpaths

Debugging of speed-limiting paths (speed paths) is a key challenge in development of Very-Large-Scale Integrated(VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speed paths under timing variations. First tim...

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Main Authors: Dehbashi, M., Fey, G.
Format: Conference Proceeding
Language:English
Subjects:
automated debugging
Circuit faults
Clocks
Debugging
Delay
failing speedpath
Integrated circuit modeling
Logic gates
timing variation
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Fey, G.
description Debugging of speed-limiting paths (speed paths) is a key challenge in development of Very-Large-Scale Integrated(VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speed paths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speed paths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites. In average, the diagnosis accuracy of 98:51% is achieved by our approach.
doi_str_mv 10.1109/ATS.2012.42
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_6394164</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6394164</ieee_id><sourcerecordid>6394164</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-c87a6fe32c7d1a3cb5e1a22e1b9e322c4ae2e20d6e19217f71994c1935072a9a3</originalsourceid><addsrcrecordid>eNotjEtPg0AURsdXIlRXLt3wBwbnzusyS1KtmjTRBPbNMFxwTFtIoQv_vST6bc7JWXyMPYDIAYR7KusqlwJkruUFSwVaZ3SBtrhkiVSI3KjCXrEUtEWlzbJrloAogCMqc8vSafoWQijhVMJseZ6Hg5-pzT6HaeZV3McwHLNnas59H499NnTZxi910Wokakc_f0137Kbz-4nu_7li9ealXr_x7cfr-7rc8ujEzEOB3nakZMAWvAqNIfBSEjRuiTJoT5KkaC2Bk4AdgnM6gFNGoPTOqxV7_LuNRLQbT_HgTz87q5wGq9Uvb0ZHSA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Automated Post-Silicon Debugging of Failing Speedpaths</title><source>IEEE Xplore All Conference Series</source><creator>Dehbashi, M. ; Fey, G.</creator><creatorcontrib>Dehbashi, M. ; Fey, G.</creatorcontrib><description>Debugging of speed-limiting paths (speed paths) is a key challenge in development of Very-Large-Scale Integrated(VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speed paths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speed paths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites. In average, the diagnosis accuracy of 98:51% is achieved by our approach.</description><identifier>ISSN: 1081-7735</identifier><identifier>ISBN: 1467345555</identifier><identifier>ISBN: 9781467345552</identifier><identifier>EISSN: 2377-5386</identifier><identifier>EISBN: 0769548768</identifier><identifier>EISBN: 9780769548760</identifier><identifier>DOI: 10.1109/ATS.2012.42</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>automated debugging ; Circuit faults ; Clocks ; Debugging ; Delay ; failing speedpath ; Integrated circuit modeling ; Logic gates ; timing variation</subject><ispartof>2012 IEEE 21st Asian Test Symposium, 2012, p.13-18</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6394164$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6394164$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Dehbashi, M.</creatorcontrib><creatorcontrib>Fey, G.</creatorcontrib><title>Automated Post-Silicon Debugging of Failing Speedpaths</title><title>2012 IEEE 21st Asian Test Symposium</title><addtitle>ats</addtitle><description>Debugging of speed-limiting paths (speed paths) is a key challenge in development of Very-Large-Scale Integrated(VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speed paths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speed paths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites. In average, the diagnosis accuracy of 98:51% is achieved by our approach.</description><subject>automated debugging</subject><subject>Circuit faults</subject><subject>Clocks</subject><subject>Debugging</subject><subject>Delay</subject><subject>failing speedpath</subject><subject>Integrated circuit modeling</subject><subject>Logic gates</subject><subject>timing variation</subject><issn>1081-7735</issn><issn>2377-5386</issn><isbn>1467345555</isbn><isbn>9781467345552</isbn><isbn>0769548768</isbn><isbn>9780769548760</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotjEtPg0AURsdXIlRXLt3wBwbnzusyS1KtmjTRBPbNMFxwTFtIoQv_vST6bc7JWXyMPYDIAYR7KusqlwJkruUFSwVaZ3SBtrhkiVSI3KjCXrEUtEWlzbJrloAogCMqc8vSafoWQijhVMJseZ6Hg5-pzT6HaeZV3McwHLNnas59H499NnTZxi910Wokakc_f0137Kbz-4nu_7li9ealXr_x7cfr-7rc8ujEzEOB3nakZMAWvAqNIfBSEjRuiTJoT5KkaC2Bk4AdgnM6gFNGoPTOqxV7_LuNRLQbT_HgTz87q5wGq9Uvb0ZHSA</recordid><startdate>201211</startdate><enddate>201211</enddate><creator>Dehbashi, M.</creator><creator>Fey, G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201211</creationdate><title>Automated Post-Silicon Debugging of Failing Speedpaths</title><author>Dehbashi, M. ; Fey, G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-c87a6fe32c7d1a3cb5e1a22e1b9e322c4ae2e20d6e19217f71994c1935072a9a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>automated debugging</topic><topic>Circuit faults</topic><topic>Clocks</topic><topic>Debugging</topic><topic>Delay</topic><topic>failing speedpath</topic><topic>Integrated circuit modeling</topic><topic>Logic gates</topic><topic>timing variation</topic><toplevel>online_resources</toplevel><creatorcontrib>Dehbashi, M.</creatorcontrib><creatorcontrib>Fey, G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dehbashi, M.</au><au>Fey, G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Automated Post-Silicon Debugging of Failing Speedpaths</atitle><btitle>2012 IEEE 21st Asian Test Symposium</btitle><stitle>ats</stitle><date>2012-11</date><risdate>2012</risdate><spage>13</spage><epage>18</epage><pages>13-18</pages><issn>1081-7735</issn><eissn>2377-5386</eissn><isbn>1467345555</isbn><isbn>9781467345552</isbn><eisbn>0769548768</eisbn><eisbn>9780769548760</eisbn><coden>IEEPAD</coden><abstract>Debugging of speed-limiting paths (speed paths) is a key challenge in development of Very-Large-Scale Integrated(VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speed paths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speed paths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites. In average, the diagnosis accuracy of 98:51% is achieved by our approach.</abstract><pub>IEEE</pub><doi>10.1109/ATS.2012.42</doi><tpages>6</tpages></addata></record>
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ispartof 2012 IEEE 21st Asian Test Symposium, 2012, p.13-18
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2377-5386
language eng
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source IEEE Xplore All Conference Series
subjects automated debugging
Circuit faults
Clocks
Debugging
Delay
failing speedpath
Integrated circuit modeling
Logic gates
timing variation
title Automated Post-Silicon Debugging of Failing Speedpaths
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T21%3A47%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Automated%20Post-Silicon%20Debugging%20of%20Failing%20Speedpaths&rft.btitle=2012%20IEEE%2021st%20Asian%20Test%20Symposium&rft.au=Dehbashi,%20M.&rft.date=2012-11&rft.spage=13&rft.epage=18&rft.pages=13-18&rft.issn=1081-7735&rft.eissn=2377-5386&rft.isbn=1467345555&rft.isbn_list=9781467345552&rft.coden=IEEPAD&rft_id=info:doi/10.1109/ATS.2012.42&rft.eisbn=0769548768&rft.eisbn_list=9780769548760&rft_dat=%3Cieee_CHZPO%3E6394164%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-c87a6fe32c7d1a3cb5e1a22e1b9e322c4ae2e20d6e19217f71994c1935072a9a3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6394164&rfr_iscdi=true