Hardware implementation of PAPR reduction scheme for OFDM system

High Peak to Average Power Ratio (PAPR) is one of the major challenges of any Orthogonal Frequency Division Multiplexing (OFDM) system. Many methods have been suggested for reducing PAPR. In this paper we design and implement an OFDM system on a FPGA along with PAPR reduction using Selected Mapping...

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Bibliographic Details
Main Authors: Kamdar, B., Shah, D., Sorathia, S., Rao, Y. S.
Format: Conference Proceeding
Language:English
Subjects:
Field programmable gate arrays
FPGA
Modulation
OFDM
Peak to average power ratio
Receivers
Resource management
Selected Mapping (SLM)
Transmitters
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Summary:High Peak to Average Power Ratio (PAPR) is one of the major challenges of any Orthogonal Frequency Division Multiplexing (OFDM) system. Many methods have been suggested for reducing PAPR. In this paper we design and implement an OFDM system on a FPGA along with PAPR reduction using Selected Mapping (SLM) technique. We analyse challenges in practical implementation of the system and also investigate the resource utilization increase as compared to a normal OFDM system.
DOI:10.1109/ICCICT.2012.6398132