Design and implementation of floating point multiplier based on Vedic Multiplication Technique

In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The mul...

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Bibliographic Details
Main Authors: Kanhe, A., Das, S. K., Singh, A. K.
Format: Conference Proceeding
Language:English
Subjects:
Adders
Computers
Conferences
Delay
Erbium
Field programmable gate arrays
Floating Point multiplier
FPGA
Urdhva-triyakbhyam sutra
Vedic Mathematics
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Summary:In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used.
DOI:10.1109/ICCICT.2012.6398204