Cell-aware Production test results from a 32-nm notebook processor

This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cell-aware (CA) library characterization and pattern-generation flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled...

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Bibliographic Details
Main Authors: Hapke, F., Reese, M., Rivers, J., Over, A., Ravikumar, V., Redemund, W., Glowatz, A., Schloeffel, J., Rajski, J.
Format: Conference Proceeding
Language:English
Subjects:
Automatic test pattern generation
Bridge circuits
Bridges
Integrated circuit interconnections
Libraries
Online Access:Request full text
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Summary:This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cell-aware (CA) library characterization and pattern-generation flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results from a 32-nm notebook processor to which CA test patterns were applied, including the defect rate reduction in PPM that was achieved after testing 800,000 parts. We also present cell-internal diagnosis and physical failure analysis results from one failing part.
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2012.6401533