Low jitter hybrid Phase Locked Loop

In this paper, we present Low jitter hybrid Phase Locked Loop (PLL). PLL are widely used in digital communication receivers because they generate a necessary clock signal, the PLLs used in communication receivers require to generate a low-jitter clock with fast frequency and phase lock. Our hybrid P...

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Bibliographic Details
Main Authors: Raj, R. P., Balaji, S., Srinivasan, K. S., Senthilnathan, S.
Format: Conference Proceeding
Language:English
Subjects:
Active inductors
Charge pumps
Clocks
CMOS integrated circuits
Jitter
LCPLL
Phase locked loops
RingPLL
Voltage-controlled oscillators
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Summary:In this paper, we present Low jitter hybrid Phase Locked Loop (PLL). PLL are widely used in digital communication receivers because they generate a necessary clock signal, the PLLs used in communication receivers require to generate a low-jitter clock with fast frequency and phase lock. Our hybrid PLL (HPLL) architecture consists of a LC-PLL followed by a Ring-PLL. The HPLL achieves improved jitter performance with a wide frequency range. The Ring PLL noise performance is improved using an LCPLL as a reference clock generator.
DOI:10.1109/EAIT.2012.6408017