Via hole technology for thin-film transistor circuits

We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis...

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Bibliographic Details
Published in:IEEE electron device letters 1997-11, Vol.18 (11), p.523-525
Main Authors: Gleskova, H., Wagner, S., Zhang, Q., Shen, D.S.
Format: Article
Language:English
Subjects:
Active matrix liquid crystal displays
Active matrix technology
Amorphous silicon
Backplanes
Circuit analysis
Delay
Glass
Liquid crystal displays
Substrates
Thin film transistors
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Summary:We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.641433