Multi-FPGA prototyping environment: Large benchmark generation and signals routing

In multi-FPGA prototyping systems for circuit verification, serialized time-multiplexed I/O technique is used because of the limited number of I/O pins of an FPGA. The verification time depends on the number of inter-FPGA signals to share the same physical wire and be time-multiplexed. In this paper...

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Bibliographic Details
Main Authors: Turki, M., Mehrez, H., Marrakchi, Z.
Format: Conference Proceeding
Language:English
Subjects:
Benchmark testing
Clocks
Computer architecture
Field programmable gate arrays
Multiplexing
Pins
Routing
Online Access:Request full text
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Summary:In multi-FPGA prototyping systems for circuit verification, serialized time-multiplexed I/O technique is used because of the limited number of I/O pins of an FPGA. The verification time depends on the number of inter-FPGA signals to share the same physical wire and be time-multiplexed. In this paper, we propose an adaptation of Pathfinder routing algorithm that minimizes the verification time of multi-FPGA systems by reducing the multiplexing ratio per physical wire. To run real experiments, we propose a large benchmark generation environment and we show that the verification system clock frequency is improved by 17% on average compared with conventional methods.
ISSN:2325-6532
2640-0472
DOI:10.1109/ReConFig.2012.6416765