Design of an optical uplink with 10 GBit/s between PCIe and MicroTCA

In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex...

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Bibliographic Details
Main Authors: Kleines, H., Wustner, P., Drochner, M., Ackens, A., Erven, W., Kammerling, P., Ramm, M., van Waasen, S.
Format: Conference Proceeding
Language:English
Subjects:
Backplanes
Data acquisition
Detectors
Field programmable gate arrays
Optical fiber communication
Transceivers
Uplink
Online Access:Request full text
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Summary:In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the FPGA implementation of the link protocol will be discussed.
DOI:10.1109/RTC.2012.6418149