A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation

• Published in: IEEE journal of solid-state circuits 2013-04, Vol.48 (4), p.932-939
• Main Authors: Arsovski, I., Hebig, T., Dobson, D., Wistort, R.
• Format: Article
• Language: English
• Subjects: Applied sciences; Computer architecture; Computers, microcomputers; deep-trench; early-predict late-correct; Electronics; Exact sciences and technology; Hardware; high performance; Input-output equipment; Integrated circuits; Integrated circuits by function (including memories and processors); low-power; Magnetic and optical mass memories; Noise; NOR; Performance evaluation; Power demand; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; sensing; Sensors; silicon-aware; Storage and reproduction of information; Switches; TCAM; Transistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2239092

A Ternary Content Addressable Memory (TCAM) uses a two-phase search operation where early prediction on its pre-search results prematurely activates the subsequent main-search operation, which is later interrupted only if the final pre-search results contradict the early prediction. This early main-search activation improves performance by 30%, while the low-probability of a late-correct has a negligible impact on power consumption. This Early-Predict Late-Correct (EPLC) sensing with silicon-aware tuning enables a high-performance TCAM compiler implemented in 32 nm High-K Metal Gate SOI process to achieve 1 Gsearch/sec throughput on a 2048×640 bit TCAM instance while consuming only 0.76 W, resulting in an energy efficiency of 0.58-fJ/bit/search. Embedded Deep-Trench (DT) capacitance reduces power supply collapse by 53% while adding only 5% area overhead for a total TCAM area of 1.56 mm 2 .