A novel multicore SDR architecture for smart vehicle systems

A transceiver architecture with multi-core software-defined radio (SDR) technology is proposed for the physical layer inner processing of IEEE 802.11p in intelligent transportation systems (ITS). By localizing the data transmissions between the adjacent digital signal processors (DSP), concatenate m...

Full description

Saved in:
Bibliographic Details
Main Authors: Yao-Hua Chen, Chia-Pin Chen, Pei-Wei Hsu, Chunfan Wei, Wei-Min Cheng, Hsun-Lun Huang, Tai-Yuan Cheng, Chen, A. Y. P.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
application-specific instruction-set processor (ASIP)
electronic system-level (ESL)
Hardware
IEEE 802.11p
intelligent transportation systems (ITS)
Quadrature amplitude modulation
Receivers
software-defined radio (SDR)
Switches
Time frequency analysis
Timing
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A transceiver architecture with multi-core software-defined radio (SDR) technology is proposed for the physical layer inner processing of IEEE 802.11p in intelligent transportation systems (ITS). By localizing the data transmissions between the adjacent digital signal processors (DSP), concatenate memories and concatenate buses are introduced to ease the bandwidth requirement for the data communication among multicores. The proposed transceiver architecture is verified by the electronic system-level (ESL) virtual platform with two application-specific instruction-set processors (ASIP). The high level power estimation results are also provided in this paper. To enhance of the channel estimation and equalization performance of IEEE 802.11p, the capability of the proposed architecture with the decision feedback algorithm is analyzed.
DOI:10.1109/ITST.2012.6425181