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OPTOBUS(TM): a parallel interconnect solution

OPTOBUS/sup TM/ is a ten channel parallel bi-directional link rated at 400 Mb/s per channel. Engineered as a DC coupled link, OPTOBUS can be used as a drop in replacement for parallel copper cable but with the ability to handle distances up to 300 meters. Electrically this places stringent constrain...

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Bibliographic Details
Main Authors: Norton, L.J., Carney, F., Denton, R.K., Fauty, J., Geist, H., James, D., Knapp, J.H., Planer, S., Raskin, G., Reyes, E., Sauvageau, J.E., Schwartz, D.B., Stradling, R., Westbrook, G.
Format: Conference Proceeding
Language:English
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Summary:OPTOBUS/sup TM/ is a ten channel parallel bi-directional link rated at 400 Mb/s per channel. Engineered as a DC coupled link, OPTOBUS can be used as a drop in replacement for parallel copper cable but with the ability to handle distances up to 300 meters. Electrically this places stringent constraints on the ICs and packaging but makes system integration simpler for the customer. Physically the user is presented with a PGA on a 14/spl times/14 array with two transceiver connectors, HIPER/sup TM/ Link, developed for OPTOBUS and designed around the MT ferrule with 62.5 /spl mu/m graded index fibers. OPTOBUS incorporates several key technologies. Vertical cavity surface emitting lasers (VCSEL) simplify the packaging since light is emitted perpendicular to the wafer surface. This feature permits wafer level probing and convenient array fabrication for parallel applications; GUIDECAST/sup TM/ is Motorola's internally developed molded-plastic waveguide array that controls the beam characteristics to meet FDA class 1 laser safety requirements and provides a robust mechanical interface. The electrical interconnection to the optoelectronic devices is achieved through a tape automated bonded lead frame. These technologies, combined with the features of the VCSEL, allows the fundamental design choice to bend the electrical path to produce an optical path parallel to the substrate surface. Custom silicon driver and receiver ICs are designed around the packaging parasitics using mature silicon processes.
ISSN:1092-8081
2766-1733
DOI:10.1109/LEOS.1997.645351