A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2013-03, Vol.32 (3), p.479-483
• Main Authors: Reviriego, P., Pontarelli, S., Maestro, J. A., Ottavi, M.
• Format: Article
• Language: English
• Subjects: Circuit design; Coders; Codes; Construction; Decoding; Delay; Double error detection; Encoders; Encoding; Error correction; Error correction & detection; Error correction codes; error correction codes (ECCs); Logic gates; Parity check codes; Registers; single error correction (SEC); Soft errors; Studies
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2012.2226585

Error correction codes (ECCs) have been used for decades to protect memories from soft errors. Single error correction (SEC) codes that can correct 1-bit error per word are a common option for memory protection. In some cases, SEC codes are extended to also provide double error detection and are known as SEC-DED codes. As technology scales, soft errors on registers also became a concern and, therefore, SEC codes are used to protect registers. The use of an ECC impacts the circuit design in terms of both delay and area. Traditional SEC or SEC-DED codes developed for memories have focused on minimizing the number of redundant bits added by the code. This is important in a memory as those bits are added to each word in the memory. However, for registers used in circuits, minimizing the delay or area introduced by the ECC can be more important. In this paper, a method to construct low delay SEC or SEC-DED codes that correct errors only on the data bits is proposed. The method is evaluated for several data block sizes, showing that the new codes offer significant delay reductions when compared with traditional SEC or SEC-DED codes. The results for the area of the encoder and decoder also show substantial savings compared to existing codes.