Technique for planning of terminal locations of leaf cells in cell-based design with routing considerations

• Main Authors: Krishna, B., Chen, C.Y.R., Sehgal, N.K.
• Format: Conference Proceeding
• Language: English
• Subjects: Delay; Design engineering; Design methodology; Educational institutions; Integrated circuit interconnections; Libraries; Logic design; Process design; Routing; Signal design
• ISSN: 1063-9667; 2380-6923
• DOI: 10.1109/ICVD.1998.646578

In any cell-based design methodology, usually, a library of cells is designed without prior knowledge of where each cell may be used. The cells from the library are placed and routed to construct the physical implementation of a circuit. The cells are designed to minimize the layout area and a little consideration is given to the location of the interface terminals. This can hinder the design of high performance circuits as the routing phase may produce interconnects with excessive signal delays. We present a new top-down design flow in which the contents of leaf cells are constructed after the cell placement has been done, with area minimization as the primary goal. Based on this placement, we design the locations of interface terminals for the leaf cells. Our proposed method optimizes leaf cell interface on the basis of cell placement and global interconnect. Our experiments show that, with this new technique, we can achieve denser and high performance layouts. Our algorithm for planning of terminal locations minimizes the number of master cells needed for multiple instances of cells, thus minimizing the cell layout effort. Our results show a reduction in total manhattan net length of 28%-75%, which implies a decrease in interconnect delays and does not cause significant increase in cell area.