Bandwidth enhancement in 3DIC CoWoS™ test using direct probe technology

Three-dimensional integrated circuit (3DIC) technologies with the vertical stacking schemes offer the promising performances but are sensitive to the post-bond probe in the testing reliability. In order to overcome this test challenge, the direct probe interface is applied and the performances of ch...

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Bibliographic Details
Main Authors: Hao Chen, Jian-Ting Chen, Shang-Ju Lee, Ken Chou, Cheng-Bin Chen, Sen-Kuei Hsu, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Bandwidth enhancement
direct probe interface
Packaging
Probes
Semiconductor device measurement
sensitivity
Silicon
Substrates
Testing
three-dimensional integrated circuit
Online Access:Request full text
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Description
Summary:Three-dimensional integrated circuit (3DIC) technologies with the vertical stacking schemes offer the promising performances but are sensitive to the post-bond probe in the testing reliability. In order to overcome this test challenge, the direct probe interface is applied and the performances of chip are also demonstrated. By using the direct probe interface, the post-bond chips have gained with 48% bandwidth enhancement and the test cost is also reduced in the whole test flow due to the reusable characteristics.
ISSN:2151-1225
2151-1233
DOI:10.1109/EDAPS.2012.6469436