Design of ADC applied in GPS receivers

This paper presents the design of an ADC (analog to digital converter) applied in a GPS receiver of which the sampling clock is 20 MHz while the input signal is 46 MHz. With the solution of the threshold-limit-speed effect, a comparator with an operating speed of 3 GHz is employed to make the ADC wo...

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Bibliographic Details
Main Authors: Haitao Liu, Qing Deng, Hao Zhang, Shushan Xie
Format: Conference Proceeding
Language:English
Subjects:
ADC
Clocks
CMOS
CMOS integrated circuits
comparator
Gain
Global Positioning System
GPS
Latches
Logic gates
Receivers
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Summary:This paper presents the design of an ADC (analog to digital converter) applied in a GPS receiver of which the sampling clock is 20 MHz while the input signal is 46 MHz. With the solution of the threshold-limit-speed effect, a comparator with an operating speed of 3 GHz is employed to make the ADC work correctly without S/H circuit. The output signals are quantified both for the sign and magnitude. At the latch output, a buffer working on the clock is used to change the output voltage level to 3.3V while the technology is 0.18-μm CMOS.
DOI:10.1109/CISP.2012.6469782