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Design of ADC applied in GPS receivers
This paper presents the design of an ADC (analog to digital converter) applied in a GPS receiver of which the sampling clock is 20 MHz while the input signal is 46 MHz. With the solution of the threshold-limit-speed effect, a comparator with an operating speed of 3 GHz is employed to make the ADC wo...
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creator | Haitao Liu Qing Deng Hao Zhang Shushan Xie |
description | This paper presents the design of an ADC (analog to digital converter) applied in a GPS receiver of which the sampling clock is 20 MHz while the input signal is 46 MHz. With the solution of the threshold-limit-speed effect, a comparator with an operating speed of 3 GHz is employed to make the ADC work correctly without S/H circuit. The output signals are quantified both for the sign and magnitude. At the latch output, a buffer working on the clock is used to change the output voltage level to 3.3V while the technology is 0.18-μm CMOS. |
doi_str_mv | 10.1109/CISP.2012.6469782 |
format | conference_proceeding |
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With the solution of the threshold-limit-speed effect, a comparator with an operating speed of 3 GHz is employed to make the ADC work correctly without S/H circuit. The output signals are quantified both for the sign and magnitude. At the latch output, a buffer working on the clock is used to change the output voltage level to 3.3V while the technology is 0.18-μm CMOS.</description><identifier>ISBN: 9781467309653</identifier><identifier>ISBN: 1467309656</identifier><identifier>EISBN: 9781467309639</identifier><identifier>EISBN: 146730963X</identifier><identifier>EISBN: 1467309648</identifier><identifier>EISBN: 9781467309646</identifier><identifier>DOI: 10.1109/CISP.2012.6469782</identifier><language>eng</language><publisher>IEEE</publisher><subject>ADC ; Clocks ; CMOS ; CMOS integrated circuits ; comparator ; Gain ; Global Positioning System ; GPS ; Latches ; Logic gates ; Receivers</subject><ispartof>2012 5th International Congress on Image and Signal Processing, 2012, p.1462-1465</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6469782$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6469782$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Haitao Liu</creatorcontrib><creatorcontrib>Qing Deng</creatorcontrib><creatorcontrib>Hao Zhang</creatorcontrib><creatorcontrib>Shushan Xie</creatorcontrib><title>Design of ADC applied in GPS receivers</title><title>2012 5th International Congress on Image and Signal Processing</title><addtitle>CISP</addtitle><description>This paper presents the design of an ADC (analog to digital converter) applied in a GPS receiver of which the sampling clock is 20 MHz while the input signal is 46 MHz. With the solution of the threshold-limit-speed effect, a comparator with an operating speed of 3 GHz is employed to make the ADC work correctly without S/H circuit. The output signals are quantified both for the sign and magnitude. At the latch output, a buffer working on the clock is used to change the output voltage level to 3.3V while the technology is 0.18-μm CMOS.</description><subject>ADC</subject><subject>Clocks</subject><subject>CMOS</subject><subject>CMOS integrated circuits</subject><subject>comparator</subject><subject>Gain</subject><subject>Global Positioning System</subject><subject>GPS</subject><subject>Latches</subject><subject>Logic gates</subject><subject>Receivers</subject><isbn>9781467309653</isbn><isbn>1467309656</isbn><isbn>9781467309639</isbn><isbn>146730963X</isbn><isbn>1467309648</isbn><isbn>9781467309646</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpVj8FKAzEURSNSUOp8gLjJyt2MeXmTl2RZploLBQu165KZeZFIrcNEBP_eAbtxdbiLey5XiFtQFYDyD816t620Al1RTd46fSGKCVCTReUJ_eW_bPBKFDm_K6WmOmmqr8X9knN6O8nPKBfLRoZhOCbuZTrJ1XYnR-44ffOYb8QshmPm4sy52D89vjbP5eZltW4WmzKBNV-lnjb62JL1QdkelHFojelaNLVGIIfROvTQ9p3zztnowFJnNDjPBMG1OBd3f97EzIdhTB9h_Dmc3-Ev0s0-vg</recordid><startdate>201210</startdate><enddate>201210</enddate><creator>Haitao Liu</creator><creator>Qing Deng</creator><creator>Hao Zhang</creator><creator>Shushan Xie</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201210</creationdate><title>Design of ADC applied in GPS receivers</title><author>Haitao Liu ; Qing Deng ; Hao Zhang ; Shushan Xie</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-2653dfb679a07d10583755cb354231683f78391bdc89887f8176c52189e61a8b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>ADC</topic><topic>Clocks</topic><topic>CMOS</topic><topic>CMOS integrated circuits</topic><topic>comparator</topic><topic>Gain</topic><topic>Global Positioning System</topic><topic>GPS</topic><topic>Latches</topic><topic>Logic gates</topic><topic>Receivers</topic><toplevel>online_resources</toplevel><creatorcontrib>Haitao Liu</creatorcontrib><creatorcontrib>Qing Deng</creatorcontrib><creatorcontrib>Hao Zhang</creatorcontrib><creatorcontrib>Shushan Xie</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore (Online service)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Haitao Liu</au><au>Qing Deng</au><au>Hao Zhang</au><au>Shushan Xie</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design of ADC applied in GPS receivers</atitle><btitle>2012 5th International Congress on Image and Signal Processing</btitle><stitle>CISP</stitle><date>2012-10</date><risdate>2012</risdate><spage>1462</spage><epage>1465</epage><pages>1462-1465</pages><isbn>9781467309653</isbn><isbn>1467309656</isbn><eisbn>9781467309639</eisbn><eisbn>146730963X</eisbn><eisbn>1467309648</eisbn><eisbn>9781467309646</eisbn><abstract>This paper presents the design of an ADC (analog to digital converter) applied in a GPS receiver of which the sampling clock is 20 MHz while the input signal is 46 MHz. With the solution of the threshold-limit-speed effect, a comparator with an operating speed of 3 GHz is employed to make the ADC work correctly without S/H circuit. The output signals are quantified both for the sign and magnitude. At the latch output, a buffer working on the clock is used to change the output voltage level to 3.3V while the technology is 0.18-μm CMOS.</abstract><pub>IEEE</pub><doi>10.1109/CISP.2012.6469782</doi><tpages>4</tpages></addata></record> |
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ispartof | 2012 5th International Congress on Image and Signal Processing, 2012, p.1462-1465 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | ADC Clocks CMOS CMOS integrated circuits comparator Gain Global Positioning System GPS Latches Logic gates Receivers |
title | Design of ADC applied in GPS receivers |
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