Improving analog/RF performance of multi-gate devices through multi-dimensional design optimization with awareness of variations and parasitics

In this paper, a new design optimization method is put forward, which can significantly improve the analog/RF performance of MG devices with impacts of parasitics and process variations considered. The gate-all-around silicon nanowire transistors (SNWTs) are taken as example, the analog/RF performan...

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Bibliographic Details
Main Authors: Yuchao Liu, Ru Huang, Runsheng Wang, Jiaojiao Ou, Yangyuan Wang
Format: Conference Proceeding
Language:English
Subjects:
Design optimization
Field effect transistors
Logic gates
Performance evaluation
Quantum capacitance
Radio frequency
Vectors
Online Access:Request full text
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Summary:In this paper, a new design optimization method is put forward, which can significantly improve the analog/RF performance of MG devices with impacts of parasitics and process variations considered. The gate-all-around silicon nanowire transistors (SNWTs) are taken as example, the analog/RF performance, such as cutoff frequency (f T ), transconductance efficiency (g m /I d ), intrinsic gain (g m /g ds ) and comprehensive figure of merit (FOM) are optimized by utilizing the proposed method. Through design optimization, higher f T of SNWTs can be obtained compared with planar FETs, which can approach the ITRS projection, manifesting the promising potential of SNWTs for high frequency circuit applications. The optimal regions of independent variable vector (X) of SNWTs are given, which can provide useful guidelines for MG device-based circuit design.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2012.6479043