Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to...

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Bibliographic Details
Main Authors: Lee, K.-W, Ohara, Y., Kiyoyama, K., Konno, S., Sato, Y., Watanabe, S., Yabata, A., Kamada, T., Bea, J.-C, Hashimoto, H., Murugesan, M., Fukushima, T., Tanaka, T., Koyanagi, M.
Format: Conference Proceeding
Language:English
Subjects:
Image processing
Image sensors
Prototypes
Silicon
Through-silicon vias
Tin
Online Access:Request full text
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Description
Summary:We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2012.6479156