Reducing substrate noise coupling in a 3D-PICS Integrated Passive Device by localized P+ guard rings

This paper presents an original concept of a P+ guard ring realized in a 300μm depth High Resistivity Silicon Substrate (HRS) in order to reduce the substrate noise coupling in a 3D-PICS Integrated Passive Device technology. Guard rings have been designed to be a reliable and efficient protection ag...

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Bibliographic Details
Main Authors: Ben Salah, Miled, Pasquet, D., Voiron, F., Descamps, P., Lefebvre, J., Lesenechal, D.
Format: Conference Proceeding
Language:English
Subjects:
Attenuation
Capacitors
coupling
Couplings
guard ring
integrated passive device
isolation
Noise
on-chip crosstalk
Phase locked loops
PICS
Silicon
substrate noise
Substrates
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Summary:This paper presents an original concept of a P+ guard ring realized in a 300μm depth High Resistivity Silicon Substrate (HRS) in order to reduce the substrate noise coupling in a 3D-PICS Integrated Passive Device technology. Guard rings have been designed to be a reliable and efficient protection against noise signals propagation. Case study presented in this work illustrates its significant role. In this paper, a 3D-PICS IPD test chip was studied as a first passive part prototype of a System-In-Package chip in combination with RF transceiver operating in the ISM band (863-870 MHz). Various configurations of the passive chip layout (including implementation of guard rings) have been characterized by Direct Power Injection. 3D-PICS electrical performances deduced from two-ports S-parameters are reported, as well as the guard rings efficiency measurements extracted from these S-parameters. Coupling isolation performances of the new integrated PICS components are found satisfactory.
ISSN:2164-2958
2164-2974
DOI:10.1109/RWS.2013.6486722