5.5GHz system z microprocessor and multi-chip module

• Main Authors: Warnock, J., Chan, Y. H., Harrer, H., Rude, D., Puri, R., Carey, S., Salem, G., Mayer, G., Yiu-Hing Chan, Mayo, M., Jatkowski, A., Strevig, G., Sigal, L., Datta, A., Gattiker, A., Bansal, A., Malone, D., Strach, T., Huajun Wen, Pak-Kin Mak, Chung-Lung Shum, Plass, D., Webb, C.
• Format: Conference Proceeding
• Language: English
• Subjects: CMOS integrated circuits; Logic gates; Program processors; Reliability; Routing; Stress; Synchronization
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2013.6487630

The new System z microprocessor chip ("CP chip") features a high-frequency processor core running at 5.5GHz in a 32nm high-κ CMOS technology [1], using 15 levels of metal. This chip is a successor to the 45nm product [2], with significant improvements made to the core and nest (i.e. the logic external to the cores) in order to increase the performance and throughput of the design. Also, special considerations were necessary to ensure robust circuit operation in the high-κ technology used for implementation. As seen in the die photo, the chip contains 6 processor cores (compared to 4 cores in the 45nm version), and a large shared 48MB DRAM L3 cache. Each core includes a pair of data and instruction L2 SRAM caches of 1MB each. In addition, the chip contains a memory control unit (MCU), an I/O bus controller (GX), and two sets of interfaces to the L4 cache chips (also in 32nm technology). The CP chip occupies 598 mm 2 , contains about 2.75B transistors, and has 1071 signal IOs.