100Gb/s ethernet chipsets in 65nm CMOS technology

This paper presents a complete design of 100GbE chipsets including gearbox TX/RX, LDD and TIA/LA arrays. Figure 7.3.1 shows the architecture, where 10×10Gb/s input data is serialized into 4×25Gb/s bit stream by a 10:4 serializer (i.e., gearbox TX). A 4-element LDD array subsequently drives 4 laser d...

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Bibliographic Details
Main Authors: Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee
Format: Conference Proceeding
Language:English
Subjects:
Arrays
Clocks
CMOS integrated circuits
Optical feedback
Optical fibers
Vertical cavity surface emitting lasers
Online Access:Request full text
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Summary:This paper presents a complete design of 100GbE chipsets including gearbox TX/RX, LDD and TIA/LA arrays. Figure 7.3.1 shows the architecture, where 10×10Gb/s input data is serialized into 4×25Gb/s bit stream by a 10:4 serializer (i.e., gearbox TX). A 4-element LDD array subsequently drives 4 laser diodes, emitting 850nm light into 4 multimode fibers (MMFs). After traveling over 100m, these optical signals are captured and transformed into electrical domain by means of photo diodes (PDs) and a TIA/LA array. A 4:10 deserializer (gear-box RX) recovers the clock and data, and restores the data sequences into 10×10Gb/s outputs. In applications, gearbox TRX and optical frontends (i.e., LDD and TIA/LA arrays) may be separated by several inches in order to fulfill system-level integration.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2013.6487663