A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS

• Main Authors: Kossel, M., Menolfi, C., Toifl, T., Francese, P. A., Brandli, M., Buchmann, P., Kull, L., Andersen, T. M., Morf, T.
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; CMOS integrated circuits; Delays; Generators; Impedance; Transmitters; Vectors
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2013.6487748

The signal integrity (SI) of double data rate (DDR) memory links is affected by signal reflections due to the multi-drop configuration of heavily loaded memory busses. Variable-impedance drivers, on-die termination (ODT), feed-forward equalization (FFE) and slew-rate (SR) control are typically implemented in DDR transmitters to address SI issues. In particular for multi-module, multi-rank configurations where speed throttling must be applied, SR control turns out to be most effective to combat reflections and crosstalk. Slewed signal edges reduce the spectral content above the bit rate frequency, whereas FFE dampens lower frequencies to compensate for channel loss, which may, however, be less of a problem at throttled data rates.