Systematic integration of flowgraph- and module-level parallelism in implementation of DSP applications on multiprocessor systems-on-chip

• Main Authors: Zheng Zhou, Chung-Ching Shen, Plishker, W., Hsiang-Huang Wu, Bhattacharyya, S. S.
• Format: Conference Proceeding
• Language: English
• ISSN: 2164-5221
• DOI: 10.1109/ICoSP.2012.6491686

Increasing use of multiprocessor system-on-chip (MPSoC) technology is an important trend in the design and implementation of signal processing systems. However, the design of efficient DSP software for MPSoC platforms involves complex inter-related steps, including data decomposition, memory management, and inter-task and inter-thread synchronization. These design steps are challenging, especially under strict constraints on performance and power consumption, and tight time to market pressures. To facilitate these steps, we have developed a new dataflow based design flow within the targeted dataflow interchange format (TDIF) design tool. Our new MPSoC-oriented design flow, called TDIF-PPG, is geared towards analysis and mapping of embedded DSP applications on MPSoCs. An important feature of TDIF-PPG is its capability to integrate graph level parallelism for DSP system flowgraphs and actor level parallelism for DSP functional modules into the application mapping processing. Here, graph level parallelism is exposed by the dataflow graph application representation in TDIF, and actor level parallelism is modeled by a novel model for multiprocessor dataflow graph implementation that we call the parallel processing group (PPG) model. We demonstrate our approach through actor and subsystem design for software defined radio.