Power performance analysis of compensated Cascaded Integrator Comb (CIC) filter in optimum computing

• Main Authors: Awasthi, V., Raj, K.
• Format: Conference Proceeding
• Language: English
• Subjects: CIC filter; Compensation Theory; Decimation filter; Fast adders; Low power design; Multirate Filtering; Redundant signed digit arithmetic; Sampling rate conversion
• DOI: 10.1109/ICPEN.2012.6492323

Decimation filter has wide application in both the analog and digital system for data rate conversion as well as filtering. This paper presents efficient compensated Cascaded Integrator Comb (CIC) decimation filter to improve the passband of interest using redundant signed digit arithmetic with its power analysis. Signed digit (SD) number systems provide the possibility of constant-time addition, where inter digit carry propagation is eliminated. A hybrid adder can add an unsigned number to a signed-digit number and hence their efficient performance greatly determines the quality of the final output of the concerned circuit. With the development of high speed processors, a tradeoff is always required between area and execution time to yield the most suitable implementation with low power consumption. The proposed work analyzed the power performance of compensated CIC decimation filter with decimation factor 64 on the bases of its On-chip leakage power and dynamic power with the variation of word length in narrow band and wide band filtering. This paper also utilized signed digit (SD) algorithm to incorporate the key features of the conventional number system with a signed digit (SD) to improve the addition time with high power constraints in an optimized fashion. CIC decimation filter with SD algorithm shows a 63.68% and 39.65% gate delay × dynamic power improvement relative to RCA and HSD fast adder algorithm respectively.