An FPGA based high speed IEEE-754 double precision floating point multiplier using Verilog

Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex-6 FPGA. In addition, the...

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Bibliographic Details
Main Authors: Ramesh, A. P., Tilak, A. V. N., Prasad, A. M.
Format: Conference Proceeding
Language:English
Subjects:
Double precision
Floating point
FPGA
IEEE-754
Lead
Multiplier
Online Access:Request full text
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Summary:Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex-6 FPGA. In addition, the proposed design is compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.
DOI:10.1109/ICEVENT.2013.6496575