Performance analysis and threshold voltage modeling of Surrounding Gate Silicon Nanowire Transistors

In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based...

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Bibliographic Details
Main Authors: Regila Manohari, M., Karthigai Pandian, M., Balamurugan, N. B.
Format: Conference Proceeding
Language:English
Subjects:
Analytical models
Drain Induced barrier lowering (DIBL)
Effective conducting path effect (ECPE)
Logic gates
Performance evaluation
Semiconductor device modeling
Short channel effect (SCE)
Silicon Nanowire Transistor (SNWT)
Surrounding gate (SG)
Threshold voltage
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Summary:In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based on various device parameters and their results are summarized and comparative study has been done. Here mainly the impact of the gate length, the surface potential, and the damaged zone length on the threshold voltage are analyzed. Parabolic potential approximation and perimeter weighted summation method are the two known methods for the threshold voltage analysis of surrounding gate MOSFETs. Simulation results are compared with the values obtained from standard numerical simulators.
DOI:10.1109/ICEVENT.2013.6496583