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Performance analysis and threshold voltage modeling of Surrounding Gate Silicon Nanowire Transistors
In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based...
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creator | Regila Manohari, M. Karthigai Pandian, M. Balamurugan, N. B. |
description | In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based on various device parameters and their results are summarized and comparative study has been done. Here mainly the impact of the gate length, the surface potential, and the damaged zone length on the threshold voltage are analyzed. Parabolic potential approximation and perimeter weighted summation method are the two known methods for the threshold voltage analysis of surrounding gate MOSFETs. Simulation results are compared with the values obtained from standard numerical simulators. |
doi_str_mv | 10.1109/ICEVENT.2013.6496583 |
format | conference_proceeding |
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B.</creator><creatorcontrib>Regila Manohari, M. ; Karthigai Pandian, M. ; Balamurugan, N. B.</creatorcontrib><description>In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based on various device parameters and their results are summarized and comparative study has been done. Here mainly the impact of the gate length, the surface potential, and the damaged zone length on the threshold voltage are analyzed. Parabolic potential approximation and perimeter weighted summation method are the two known methods for the threshold voltage analysis of surrounding gate MOSFETs. Simulation results are compared with the values obtained from standard numerical simulators.</description><identifier>ISBN: 1467353000</identifier><identifier>ISBN: 9781467353007</identifier><identifier>EISBN: 9781467352994</identifier><identifier>EISBN: 1467352993</identifier><identifier>EISBN: 9781467353014</identifier><identifier>EISBN: 1467353019</identifier><identifier>DOI: 10.1109/ICEVENT.2013.6496583</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analytical models ; Drain Induced barrier lowering (DIBL) ; Effective conducting path effect (ECPE) ; Logic gates ; Performance evaluation ; Semiconductor device modeling ; Short channel effect (SCE) ; Silicon Nanowire Transistor (SNWT) ; Surrounding gate (SG) ; Threshold voltage</subject><ispartof>2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6496583$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27923,54918</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6496583$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Regila Manohari, M.</creatorcontrib><creatorcontrib>Karthigai Pandian, M.</creatorcontrib><creatorcontrib>Balamurugan, N. B.</creatorcontrib><title>Performance analysis and threshold voltage modeling of Surrounding Gate Silicon Nanowire Transistors</title><title>2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)</title><addtitle>ICEVENT</addtitle><description>In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based on various device parameters and their results are summarized and comparative study has been done. Here mainly the impact of the gate length, the surface potential, and the damaged zone length on the threshold voltage are analyzed. Parabolic potential approximation and perimeter weighted summation method are the two known methods for the threshold voltage analysis of surrounding gate MOSFETs. Simulation results are compared with the values obtained from standard numerical simulators.</description><subject>Analytical models</subject><subject>Drain Induced barrier lowering (DIBL)</subject><subject>Effective conducting path effect (ECPE)</subject><subject>Logic gates</subject><subject>Performance evaluation</subject><subject>Semiconductor device modeling</subject><subject>Short channel effect (SCE)</subject><subject>Silicon Nanowire Transistor (SNWT)</subject><subject>Surrounding gate (SG)</subject><subject>Threshold voltage</subject><isbn>1467353000</isbn><isbn>9781467353007</isbn><isbn>9781467352994</isbn><isbn>1467352993</isbn><isbn>9781467353014</isbn><isbn>1467353019</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkMFOAjEURWuMiYp8gS76A4ztvHZKl4YgkBA0Ad2SzvQVaobWtIOGv3cMrO65m5PcS8gTZwXnTD8vJtPP6WpTlIxDUQldyTFckaFWYy4qBbLUWlyT-3MBxtgtGeb81QPTqgQt74h9x-RiOpjQIDXBtKfscw-WdvuEeR9bS39i25kd0kO02Pqwo9HR9TGleAz2v85Mh3TtW9_EQFcmxF-fkG6SCb2riyk_kBtn2ozDSw7Ix-t0M5mPlm-zxeRlOfJcyW5Us7IE2dRCAVTWoWTorBUanayMBaeFQmjGtWBY24rVSjUM0HJmVT9ZAgzI49nrEXH7nfzBpNP2cgz8AfnyWgM</recordid><startdate>201301</startdate><enddate>201301</enddate><creator>Regila Manohari, M.</creator><creator>Karthigai Pandian, M.</creator><creator>Balamurugan, N. B.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201301</creationdate><title>Performance analysis and threshold voltage modeling of Surrounding Gate Silicon Nanowire Transistors</title><author>Regila Manohari, M. ; Karthigai Pandian, M. ; Balamurugan, N. B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-b02235cb47336dfe50efdd49ef56ad3f947e3c8b40ebd60b77c03ed10d7978533</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Analytical models</topic><topic>Drain Induced barrier lowering (DIBL)</topic><topic>Effective conducting path effect (ECPE)</topic><topic>Logic gates</topic><topic>Performance evaluation</topic><topic>Semiconductor device modeling</topic><topic>Short channel effect (SCE)</topic><topic>Silicon Nanowire Transistor (SNWT)</topic><topic>Surrounding gate (SG)</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Regila Manohari, M.</creatorcontrib><creatorcontrib>Karthigai Pandian, M.</creatorcontrib><creatorcontrib>Balamurugan, N. B.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Regila Manohari, M.</au><au>Karthigai Pandian, M.</au><au>Balamurugan, N. B.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Performance analysis and threshold voltage modeling of Surrounding Gate Silicon Nanowire Transistors</atitle><btitle>2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)</btitle><stitle>ICEVENT</stitle><date>2013-01</date><risdate>2013</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>1467353000</isbn><isbn>9781467353007</isbn><eisbn>9781467352994</eisbn><eisbn>1467352993</eisbn><eisbn>9781467353014</eisbn><eisbn>1467353019</eisbn><abstract>In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based on various device parameters and their results are summarized and comparative study has been done. Here mainly the impact of the gate length, the surface potential, and the damaged zone length on the threshold voltage are analyzed. Parabolic potential approximation and perimeter weighted summation method are the two known methods for the threshold voltage analysis of surrounding gate MOSFETs. Simulation results are compared with the values obtained from standard numerical simulators.</abstract><pub>IEEE</pub><doi>10.1109/ICEVENT.2013.6496583</doi><tpages>4</tpages></addata></record> |
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ispartof | 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013, p.1-4 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Analytical models Drain Induced barrier lowering (DIBL) Effective conducting path effect (ECPE) Logic gates Performance evaluation Semiconductor device modeling Short channel effect (SCE) Silicon Nanowire Transistor (SNWT) Surrounding gate (SG) Threshold voltage |
title | Performance analysis and threshold voltage modeling of Surrounding Gate Silicon Nanowire Transistors |
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