High performance double gate silicon nanowire transistors

This paper deals with the study of modelling double gate silicon nanowire transistors. The scaling of nanowire transistors to 10nm and below is discussed for acceptable short-channel effects and the quantum mechanical effects caused by ultrathin silicon devices considered in modelling the threshold...

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Bibliographic Details
Main Authors: Sagana Gandi, M., Karthigai Pandian, M., Balamurugan, N. B.
Format: Conference Proceeding
Language:English
Subjects:
Double Gate (DG)
Electric potential
Equations
Inversion-charge
Logic gates
Mathematical model
MOSFET
Nanoscale devices
Quantum Mechanical Effects (QME)
Scaling
Semiconductor process modeling
Short Channel Effects (SCE)
Silicon Nanowire Transistor (SiNW)
Threshold voltage
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Summary:This paper deals with the study of modelling double gate silicon nanowire transistors. The scaling of nanowire transistors to 10nm and below is discussed for acceptable short-channel effects and the quantum mechanical effects caused by ultrathin silicon devices considered in modelling the threshold voltage is studied. Similarly, the variation of threshold voltage with different doping density, channel length, channel thickness and oxide thickness of DG MOSFET are analysed. The inversion charge and electrical potential along the channel of double gate MOSFET are also discussed in this paper. These approaches analysed are based upon the analytical solutions of Schrödinger and Poisson equations solved in the silicon channel. The simulation results obtained from various methodologies are compared to analyze the performance of the DG MOSFETs.
DOI:10.1109/ICEVENT.2013.6496585