A low power single phase clock distribution using VLSI technology

The clock distribution network consumes nearly 70% of the total power consumed by the IC since this is the only signal which has the highest switching activity. Normally for a multi clock domain network we develop a multiple PLL to cater the need, this project aim for developing a low power single c...

Full description

Saved in:
Bibliographic Details
Main Authors: Indhumathi, A., Sathishkumar, A.
Format: Conference Proceeding
Language:English
Subjects:
CMOS integrated circuits
Educational institutions
Frequency conversion
Frequency synthesizers
Logic gates
Switches
Wireless LAN
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 5
container_issue
container_start_page 1
container_title
container_volume
creator Indhumathi, A.
Sathishkumar, A.
description The clock distribution network consumes nearly 70% of the total power consumed by the IC since this is the only signal which has the highest switching activity. Normally for a multi clock domain network we develop a multiple PLL to cater the need, this project aim for developing a low power single clock multiband network which will supply for the multi clock domain network. This project is highly useful and recommended for communication applications like Bluetooth, Zigbee. WLAN frequency synthesizers are proposed based on pulse-swallow topology and the designed is modeled using Verilog simulated using Modelsim and implemented in Xilinx.
doi_str_mv 10.1109/ICEVENT.2013.6496592
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6496592</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6496592</ieee_id><sourcerecordid>6496592</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-5f1091d1f9af9c731698f02d87d362a7c648e0477a174f391ddd51ffdcdd20c43</originalsourceid><addsrcrecordid>eNotj81Kw0AAhFdEUGueQA_7Aon7v9ljCNEGgh6svZZ1f9rVmC3ZlNK3N9KeZgY-hhkAnjAqMEbqua2bdfO2KgjCtBBMCa7IFciULDETknKiFLsG9-dAEUK3IEvpezZISUIVvwNVBft4hPt4dCNMYdj2Du53Ojlo-mh-oA1pGsPXYQpxgId_AK67jxZOzuyG2Mft6QHceN0nl110AT5fmlW9zLv317auujxgyaec-3kxttgr7ZWRFAtVekRsKS0VREsjWOkQk1JjyTydUWs59t4aawkyjC7A47k3OOc2-zH86vG0ubymf-mUS5o</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A low power single phase clock distribution using VLSI technology</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Indhumathi, A. ; Sathishkumar, A.</creator><creatorcontrib>Indhumathi, A. ; Sathishkumar, A.</creatorcontrib><description>The clock distribution network consumes nearly 70% of the total power consumed by the IC since this is the only signal which has the highest switching activity. Normally for a multi clock domain network we develop a multiple PLL to cater the need, this project aim for developing a low power single clock multiband network which will supply for the multi clock domain network. This project is highly useful and recommended for communication applications like Bluetooth, Zigbee. WLAN frequency synthesizers are proposed based on pulse-swallow topology and the designed is modeled using Verilog simulated using Modelsim and implemented in Xilinx.</description><identifier>ISBN: 1467353000</identifier><identifier>ISBN: 9781467353007</identifier><identifier>EISBN: 9781467352994</identifier><identifier>EISBN: 1467352993</identifier><identifier>EISBN: 9781467353014</identifier><identifier>EISBN: 1467353019</identifier><identifier>DOI: 10.1109/ICEVENT.2013.6496592</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS integrated circuits ; Educational institutions ; Frequency conversion ; Frequency synthesizers ; Logic gates ; Switches ; Wireless LAN</subject><ispartof>2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013, p.1-5</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6496592$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6496592$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Indhumathi, A.</creatorcontrib><creatorcontrib>Sathishkumar, A.</creatorcontrib><title>A low power single phase clock distribution using VLSI technology</title><title>2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)</title><addtitle>ICEVENT</addtitle><description>The clock distribution network consumes nearly 70% of the total power consumed by the IC since this is the only signal which has the highest switching activity. Normally for a multi clock domain network we develop a multiple PLL to cater the need, this project aim for developing a low power single clock multiband network which will supply for the multi clock domain network. This project is highly useful and recommended for communication applications like Bluetooth, Zigbee. WLAN frequency synthesizers are proposed based on pulse-swallow topology and the designed is modeled using Verilog simulated using Modelsim and implemented in Xilinx.</description><subject>CMOS integrated circuits</subject><subject>Educational institutions</subject><subject>Frequency conversion</subject><subject>Frequency synthesizers</subject><subject>Logic gates</subject><subject>Switches</subject><subject>Wireless LAN</subject><isbn>1467353000</isbn><isbn>9781467353007</isbn><isbn>9781467352994</isbn><isbn>1467352993</isbn><isbn>9781467353014</isbn><isbn>1467353019</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj81Kw0AAhFdEUGueQA_7Aon7v9ljCNEGgh6svZZ1f9rVmC3ZlNK3N9KeZgY-hhkAnjAqMEbqua2bdfO2KgjCtBBMCa7IFciULDETknKiFLsG9-dAEUK3IEvpezZISUIVvwNVBft4hPt4dCNMYdj2Du53Ojlo-mh-oA1pGsPXYQpxgId_AK67jxZOzuyG2Mft6QHceN0nl110AT5fmlW9zLv317auujxgyaec-3kxttgr7ZWRFAtVekRsKS0VREsjWOkQk1JjyTydUWs59t4aawkyjC7A47k3OOc2-zH86vG0ubymf-mUS5o</recordid><startdate>201301</startdate><enddate>201301</enddate><creator>Indhumathi, A.</creator><creator>Sathishkumar, A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201301</creationdate><title>A low power single phase clock distribution using VLSI technology</title><author>Indhumathi, A. ; Sathishkumar, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-5f1091d1f9af9c731698f02d87d362a7c648e0477a174f391ddd51ffdcdd20c43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CMOS integrated circuits</topic><topic>Educational institutions</topic><topic>Frequency conversion</topic><topic>Frequency synthesizers</topic><topic>Logic gates</topic><topic>Switches</topic><topic>Wireless LAN</topic><toplevel>online_resources</toplevel><creatorcontrib>Indhumathi, A.</creatorcontrib><creatorcontrib>Sathishkumar, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Indhumathi, A.</au><au>Sathishkumar, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A low power single phase clock distribution using VLSI technology</atitle><btitle>2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)</btitle><stitle>ICEVENT</stitle><date>2013-01</date><risdate>2013</risdate><spage>1</spage><epage>5</epage><pages>1-5</pages><isbn>1467353000</isbn><isbn>9781467353007</isbn><eisbn>9781467352994</eisbn><eisbn>1467352993</eisbn><eisbn>9781467353014</eisbn><eisbn>1467353019</eisbn><abstract>The clock distribution network consumes nearly 70% of the total power consumed by the IC since this is the only signal which has the highest switching activity. Normally for a multi clock domain network we develop a multiple PLL to cater the need, this project aim for developing a low power single clock multiband network which will supply for the multi clock domain network. This project is highly useful and recommended for communication applications like Bluetooth, Zigbee. WLAN frequency synthesizers are proposed based on pulse-swallow topology and the designed is modeled using Verilog simulated using Modelsim and implemented in Xilinx.</abstract><pub>IEEE</pub><doi>10.1109/ICEVENT.2013.6496592</doi><tpages>5</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 1467353000
ispartof 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013, p.1-5
issn
language eng
recordid cdi_ieee_primary_6496592
source IEEE Electronic Library (IEL) Conference Proceedings
subjects CMOS integrated circuits
Educational institutions
Frequency conversion
Frequency synthesizers
Logic gates
Switches
Wireless LAN
title A low power single phase clock distribution using VLSI technology
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-30T03%3A01%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20low%20power%20single%20phase%20clock%20distribution%20using%20VLSI%20technology&rft.btitle=2013%20International%20Conference%20on%20Emerging%20Trends%20in%20VLSI,%20Embedded%20System,%20Nano%20Electronics%20and%20Telecommunication%20System%20(ICEVENT)&rft.au=Indhumathi,%20A.&rft.date=2013-01&rft.spage=1&rft.epage=5&rft.pages=1-5&rft.isbn=1467353000&rft.isbn_list=9781467353007&rft_id=info:doi/10.1109/ICEVENT.2013.6496592&rft.eisbn=9781467352994&rft.eisbn_list=1467352993&rft.eisbn_list=9781467353014&rft.eisbn_list=1467353019&rft_dat=%3Cieee_6IE%3E6496592%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-5f1091d1f9af9c731698f02d87d362a7c648e0477a174f391ddd51ffdcdd20c43%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6496592&rfr_iscdi=true