A Protocol Independent Test Design for Quick Determination of Incoherency in CMPs' Cache

The data coherence in the cache systems of CMPs (Chip Multi-Processors) is to be more accurate and reliable. The conventional solutions for verification of cache coherence targeting small systems are not so effective in CMPs. The CMPs cache system further demands a protocol independent test logic. I...

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Bibliographic Details
Main Authors: Dalui, M., Sikdar, B. K.
Format: Conference Proceeding
Language:English
Subjects:
Automata
Cache coherence
CMP
Coherence
Coherence controller
Computational modeling
Fault detection
Hardware
MESI
MOESI
Program processors
Protocols
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Description
Summary:The data coherence in the cache systems of CMPs (Chip Multi-Processors) is to be more accurate and reliable. The conventional solutions for verification of cache coherence targeting small systems are not so effective in CMPs. The CMPs cache system further demands a protocol independent test logic. In this work, we propose an effective solution to the issue through introduction of highly efficient test logic (fault detection unit). The design is developed around a special class of Cellular Automata (CA) referred to as the SACA (single length single cycle attractor cellular automata). The SACA is introduced to identify the inconsistencies in cache line states of processors' private caches catering the MSI/MESI/MOESI protocols. The SACA theory developed for the design enables protocol independent verification hardware logic to realize quick decision on the accurate cache coherency in CMPs.
ISSN:2166-0662
2166-0670
DOI:10.1109/ISMS.2013.92