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Extensible processor speeds up IP lookup
With ever increasing internet link speeds and growing routing table size, IP address lookup has been major performance bottleneck for routers. Traditionally ASIC or CAM based solutions are used to achieve the demanding performance requirements of IP lookup. These solutions are costly as well as lack...
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creator | Gautam, P. K. Jagtap, M. K. P. |
description | With ever increasing internet link speeds and growing routing table size, IP address lookup has been major performance bottleneck for routers. Traditionally ASIC or CAM based solutions are used to achieve the demanding performance requirements of IP lookup. These solutions are costly as well as lack programmability, scalability and flexibility. Upgradation of services and protocols necessitates programmability of routers. In this paper, we present a cost effective and flexible solution to achieve fast IP lookup using extensible and configurable processor. Configurable and extensible processor can be tuned by the designer to accelerate applications by selecting suitable processor parameters, adding new instructions and hardware. We have used Eatherton Tree Bitmap algorithms for address lookup and developed instructions that are optimized to yield large performance improvements. With the addition of these newly created instructions, a lookup performance of 17.5 Million lookups per second (Mlps) is achieved for processor running at 500 Mhz. |
doi_str_mv | 10.1109/ICON.2012.6506593 |
format | conference_proceeding |
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K. ; Jagtap, M. K. P.</creator><creatorcontrib>Gautam, P. K. ; Jagtap, M. K. P.</creatorcontrib><description>With ever increasing internet link speeds and growing routing table size, IP address lookup has been major performance bottleneck for routers. Traditionally ASIC or CAM based solutions are used to achieve the demanding performance requirements of IP lookup. These solutions are costly as well as lack programmability, scalability and flexibility. Upgradation of services and protocols necessitates programmability of routers. In this paper, we present a cost effective and flexible solution to achieve fast IP lookup using extensible and configurable processor. Configurable and extensible processor can be tuned by the designer to accelerate applications by selecting suitable processor parameters, adding new instructions and hardware. We have used Eatherton Tree Bitmap algorithms for address lookup and developed instructions that are optimized to yield large performance improvements. With the addition of these newly created instructions, a lookup performance of 17.5 Million lookups per second (Mlps) is achieved for processor running at 500 Mhz.</description><identifier>ISSN: 1531-2216</identifier><identifier>ISBN: 9781467345217</identifier><identifier>ISBN: 1467345210</identifier><identifier>EISSN: 2332-5798</identifier><identifier>EISBN: 9781467345224</identifier><identifier>EISBN: 1467345229</identifier><identifier>EISBN: 9781467345231</identifier><identifier>EISBN: 1467345237</identifier><identifier>DOI: 10.1109/ICON.2012.6506593</identifier><language>eng</language><publisher>IEEE</publisher><subject>Algorithm design and analysis ; ASIP ; configurable processor ; Hardware ; Indexes ; IP address lookup ; IP networks ; Memory management ; Routing ; Tree Bitmap</subject><ispartof>2012 18th IEEE International Conference on Networks (ICON), 2012, p.411-415</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6506593$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6506593$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Gautam, P. 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We have used Eatherton Tree Bitmap algorithms for address lookup and developed instructions that are optimized to yield large performance improvements. With the addition of these newly created instructions, a lookup performance of 17.5 Million lookups per second (Mlps) is achieved for processor running at 500 Mhz.</description><subject>Algorithm design and analysis</subject><subject>ASIP</subject><subject>configurable processor</subject><subject>Hardware</subject><subject>Indexes</subject><subject>IP address lookup</subject><subject>IP networks</subject><subject>Memory management</subject><subject>Routing</subject><subject>Tree Bitmap</subject><issn>1531-2216</issn><issn>2332-5798</issn><isbn>9781467345217</isbn><isbn>1467345210</isbn><isbn>9781467345224</isbn><isbn>1467345229</isbn><isbn>9781467345231</isbn><isbn>1467345237</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpVj0tLw0AURscXGGt_gLjJ0k3i3HvnuZRSNVCsC12XOHMHotGETAv67y3YjXDgLA588AlxBbIGkP62WayfapSAtdHSaE9HYu6tA2UsKY2ojkWBRFhp693Jvwb2VBSgCSpEMOfiIud3KVGiVYW4WX5v-St3bz2X4zQEznmYyjwyx1zuxrJ5Lvth-NiNl-IstX3m-cEz8Xq_fFk8Vqv1Q7O4W1UdWL2tVETlAoWwFxmLnKRtKbFuQ3QmJY3etR5chKC8AVYKIrkkHVq7J9JMXP_tdsy8Gafus51-NofT9AvNz0So</recordid><startdate>201212</startdate><enddate>201212</enddate><creator>Gautam, P. K.</creator><creator>Jagtap, M. K. P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201212</creationdate><title>Extensible processor speeds up IP lookup</title><author>Gautam, P. K. ; Jagtap, M. K. P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-4d248c3cc2483672ef07a3fe5acd86ff5298a918d1c4961e441d38f08277277d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Algorithm design and analysis</topic><topic>ASIP</topic><topic>configurable processor</topic><topic>Hardware</topic><topic>Indexes</topic><topic>IP address lookup</topic><topic>IP networks</topic><topic>Memory management</topic><topic>Routing</topic><topic>Tree Bitmap</topic><toplevel>online_resources</toplevel><creatorcontrib>Gautam, P. K.</creatorcontrib><creatorcontrib>Jagtap, M. K. P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gautam, P. K.</au><au>Jagtap, M. K. P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Extensible processor speeds up IP lookup</atitle><btitle>2012 18th IEEE International Conference on Networks (ICON)</btitle><stitle>ICON</stitle><date>2012-12</date><risdate>2012</risdate><spage>411</spage><epage>415</epage><pages>411-415</pages><issn>1531-2216</issn><eissn>2332-5798</eissn><isbn>9781467345217</isbn><isbn>1467345210</isbn><eisbn>9781467345224</eisbn><eisbn>1467345229</eisbn><eisbn>9781467345231</eisbn><eisbn>1467345237</eisbn><abstract>With ever increasing internet link speeds and growing routing table size, IP address lookup has been major performance bottleneck for routers. Traditionally ASIC or CAM based solutions are used to achieve the demanding performance requirements of IP lookup. These solutions are costly as well as lack programmability, scalability and flexibility. Upgradation of services and protocols necessitates programmability of routers. In this paper, we present a cost effective and flexible solution to achieve fast IP lookup using extensible and configurable processor. Configurable and extensible processor can be tuned by the designer to accelerate applications by selecting suitable processor parameters, adding new instructions and hardware. We have used Eatherton Tree Bitmap algorithms for address lookup and developed instructions that are optimized to yield large performance improvements. With the addition of these newly created instructions, a lookup performance of 17.5 Million lookups per second (Mlps) is achieved for processor running at 500 Mhz.</abstract><pub>IEEE</pub><doi>10.1109/ICON.2012.6506593</doi><tpages>5</tpages></addata></record> |
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ispartof | 2012 18th IEEE International Conference on Networks (ICON), 2012, p.411-415 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Algorithm design and analysis ASIP configurable processor Hardware Indexes IP address lookup IP networks Memory management Routing Tree Bitmap |
title | Extensible processor speeds up IP lookup |
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