A new leakage reduction method for ultra low power VLSI design for portable devices

• Main Authors: Chowdhury, A. J., Rizwan, Md S., Nibir, S. J., Siddique, Md R. A.
• Format: Conference Proceeding
• Language: English
• Subjects: Low Power VLSI design; Sleep transistor; Stack effect; State saving technique; Variable body biasing
• DOI: 10.1109/ICPCES.2012.6508074

Portable electronic devices are integral components in our quotidian life. These devices require charging after a certain amount of usage time. Most of the time during discharging cycle, they remain idle or inactive. If these devices are not in active use, why does the battery discharge? The answer is leakage power consumption. At present the power density in CMOS integrated circuits has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. With downward scaling of technology, static power consumption is becoming more dominant. It is challenging for the circuit designers to balance both scaling and low static power demands. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using stacked sleep transistor without being penalized in power delay product requirement and circuit performance.