Efficient cache architectures for reliable hybrid voltage operation using EDC codes

Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 €) required for new market segments such as body, urban life and environment monitoring. Caches have been shown to be the highest energy and area consumer in those chips. This pa...

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Bibliographic Details
Main Authors: Maric, Bojan, Abella, Jaume, Valero, Mateo
Format: Conference Proceeding
Language:English
Subjects:
Benchmark testing
Caches
Computer architecture
Encoding
Low Energy
Real-Time
Reliability
Robustness
SRAM cells
Transistors
Online Access:Request full text
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Summary:Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 €) required for new market segments such as body, urban life and environment monitoring. Caches have been shown to be the highest energy and area consumer in those chips. This paper proposes a novel, hybrid-operation (high Vcc, ultra-low Vcc), single-V cc domain cache architecture based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with Error Detection and Correction (EDC) features for high reliability and performance predictability. Our architecture is proven to largely outperform existing solutions in terms of energy and area.
ISSN:1530-1591
1558-1101
DOI:10.7873/DATE.2013.193