A fast and accurate methodology for power estimation and reduction of programmable architectures

We present a power optimization methodology that provides a fast and accurate power model for programmable architectures. The approach is based on a new tool that estimates power consumption from a register transfer level (RTL) module description, activity files and technology library. It efficientl...

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Bibliographic Details
Main Authors: Piriou, Erwan, David, Raphael, Rahim, Fahim, Rahim, Solaiman
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Estimation
Logic gates
Power demand
Radio frequency
Registers
Space exploration
Online Access:Request full text
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Description
Summary:We present a power optimization methodology that provides a fast and accurate power model for programmable architectures. The approach is based on a new tool that estimates power consumption from a register transfer level (RTL) module description, activity files and technology library. It efficiently provides an instruction-level accurate power model and allows design space exploration for the register file. We demonstrate a 19% improvement for a standard RISC processor.
ISSN:1530-1591
1558-1101
DOI:10.7873/DATE.2013.220