Transistor gating: Reduction of leakage current and power in full subtractor circuit

In this paper low-power design techniques proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating transistor grating technology. In low-power design for circuit to reduce the power supply voltage and this requires the transistor thre...

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Bibliographic Details
Main Authors: Gautam, M., Akashe, S.
Format: Conference Proceeding
Language:English
Subjects:
CMOS
CMOS integrated circuits
CMOS technology
Full subtractor
leakage current
Leakage currents
low power
Switching circuits
Threshold voltage
transistor grating
Transistors
Very large scale integration
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Summary:In this paper low-power design techniques proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating transistor grating technology. In low-power design for circuit to reduce the power supply voltage and this requires the transistor threshold voltages to also be reduced to maintain throughput and noise margins., this increases the subthreshold leakage current in p and n MOSFETs. this begins to increase the overall power in digital circuits. How-ever, this increases the subthreshold leakage current of p and n MOSFETs, which starts to set the power savings obtained from power supply reduction. In transistor grating technology two sleep transistors PMOS and NMOS are inserted in between the supply voltage and ground. A PMOS is inserted in between pull-up network and network output and a NMOS is inserted in between pull-down network and ground. During standby mode both sleep transistor are turned off. By applying this technique reduction in leakage current is 17.58% and power is 24.38%. The tool used is CADENCE VIRTUOSO for schematic simulation. The simulation technology used is 45nm.
DOI:10.1109/IAdCC.2013.6514451