Transistor-level optimization of CMOS complex gates

This paper presents a new methodology to generate efficient transistor networks. Transistor-level optimization consists in an effective possibility to increase design quality when generating CMOS logic gates to be inserted in standard cell libraries. Starting from an input ISOP, the proposed method...

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Bibliographic Details
Main Authors: Possani, V. N., Marques, F. S., da Rosa Junior, L. S., Callegaro, V., Reis, A. I., Ribas, R. P.
Format: Conference Proceeding
Language:English
Subjects:
Boolean functions
Equations
Kernel
Logic gates
Optimization
Switches
Transistors
Online Access:Request full text
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Summary:This paper presents a new methodology to generate efficient transistor networks. Transistor-level optimization consists in an effective possibility to increase design quality when generating CMOS logic gates to be inserted in standard cell libraries. Starting from an input ISOP, the proposed method is able to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The experiments performed over the set of 4-input P-class Booleans functions have demonstrated the efficiency of the proposed approach.
DOI:10.1109/LASCAS.2013.6519029