C-slow retimed parallel histogram architectures for consumer imaging devices

A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher t...

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Bibliographic Details
Published in:IEEE transactions on consumer electronics 2013-05, Vol.59 (2), p.291-295
Main Authors: Cadenas, J., Sherratt, R. S., Huerta, P., Wen-Chung Kao, Megson, G. M.
Format: Article
Language:English
Subjects:
Architecture
Arrays
Clocks
Construction
Consumer electronics
Digital Imaging
Educational institutions
Electronics
FPGA
Histograms
Image Processing
Parallel Histograms
Pipelined Array
Registers
Sampling
Sensors
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Summary:A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.
ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2013.6531108