Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies

Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and...

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Bibliographic Details
Main Authors: Kerber, A., Nigam, T.
Format: Conference Proceeding
Language:English
Subjects:
BTI variability
CMOS
Data models
Earth Observing System
Gaussian distribution
high-k dielectrics
Logic gates
metal gate
Random access memory
Semiconductor device modeling
SRAM
Stress
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Description
Summary:Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero V T and ΔV T and illustrate the minor impact of BTI induced variability on post-stress V T distributions relevant for modeling the circuit aging.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2013.6531959