Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied and excellent reliability is demonstrated. In order...

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Bibliographic Details
Main Authors: Rahman, A., Bai, P., Curello, G., Hicks, J., Jan, C.-H, Jamil, M., Park, J., Phoa, K., Rahman, M. S., Tsai, C., Woolery, B., Yeh, J.-Y
Format: Conference Proceeding
Language:English
Subjects:
breakdown
BTI
CMOS
Degradation
Dielectrics
High-K dielectric
Logic gates
metal gate
MOS devices
Reliability
SILC
SoC
System-on-chip
TDDB
Transistors
tri-gate
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Summary:Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied and excellent reliability is demonstrated. In order to simultaneously integrate logic and HV 3-D tri-gate transistors with robust reliability, the importance of process optimization is emphasized.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2013.6532105