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Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application
Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied and excellent reliability is demonstrated. In order...
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| container_end_page | PI.2.6 |
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| creator | Rahman, A. Bai, P. Curello, G. Hicks, J. Jan, C.-H Jamil, M. Park, J. Phoa, K. Rahman, M. S. Tsai, C. Woolery, B. Yeh, J.-Y |
| description | Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied and excellent reliability is demonstrated. In order to simultaneously integrate logic and HV 3-D tri-gate transistors with robust reliability, the importance of process optimization is emphasized. |
| doi_str_mv | 10.1109/IRPS.2013.6532105 |
| format | conference_proceeding |
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S.</creatorcontrib><creatorcontrib>Tsai, C.</creatorcontrib><creatorcontrib>Woolery, B.</creatorcontrib><creatorcontrib>Yeh, J.-Y</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rahman, A.</au><au>Bai, P.</au><au>Curello, G.</au><au>Hicks, J.</au><au>Jan, C.-H</au><au>Jamil, M.</au><au>Park, J.</au><au>Phoa, K.</au><au>Rahman, M. S.</au><au>Tsai, C.</au><au>Woolery, B.</au><au>Yeh, J.-Y</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application</atitle><btitle>2013 IEEE International Reliability Physics Symposium (IRPS)</btitle><stitle>IRPS</stitle><date>2013-04</date><risdate>2013</risdate><spage>PI.2.1</spage><epage>PI.2.6</epage><pages>PI.2.1-PI.2.6</pages><issn>1541-7026</issn><eissn>1938-1891</eissn><isbn>9781479901128</isbn><isbn>1479901121</isbn><eisbn>9781479901111</eisbn><eisbn>147990113X</eisbn><eisbn>1479901113</eisbn><eisbn>9781479901135</eisbn><abstract>Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied and excellent reliability is demonstrated. In order to simultaneously integrate logic and HV 3-D tri-gate transistors with robust reliability, the importance of process optimization is emphasized.</abstract><pub>IEEE</pub><doi>10.1109/IRPS.2013.6532105</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1541-7026 |
| ispartof | 2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.PI.2.1-PI.2.6 |
| issn | 1541-7026 1938-1891 |
| language | eng |
| recordid | cdi_ieee_primary_6532105 |
| source | IEEE Xplore All Conference Series |
| subjects | breakdown BTI CMOS Degradation Dielectrics High-K dielectric Logic gates metal gate MOS devices Reliability SILC SoC System-on-chip TDDB Transistors tri-gate |
| title | Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application |
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