A background calibration technique for fully dynamic flash ADCs

A fully dynamic flash ADC is attractive for its low-power and low-input capacitance natures. It has minimal static current consumption, and its power and area costs diminish as process advances. However, the comparators thresholds, which are set by the built-in offsets, are sensitive to supply and t...

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Bibliographic Details
Main Authors: Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Calibration
Latches
Modulation
Power dissipation
Resistors
Temperature measurement
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Summary:A fully dynamic flash ADC is attractive for its low-power and low-input capacitance natures. It has minimal static current consumption, and its power and area costs diminish as process advances. However, the comparators thresholds, which are set by the built-in offsets, are sensitive to supply and temperature drifts. This threshold variation may result in up to ±20% ADC gain error with ENOB degradation. This paper presents a calibration scheme used to restore the ADC performance without interrupting the normal operation. This technique enables the practical use of fully dynamic flash ADCs and is demonstrated in the quantizer design of a continuous-time ΔΣ modulator. The quantizer accounts for 0.3mW of 3.74mW total power dissipation and relaxes the opamp requirements. The modulator achieves 75.6dB SNDR and 82dB DR over a 10MHz BW, leading to an Walden FoM of 38fJ/conv-step.
DOI:10.1109/VLDI-DAT.2013.6533857