A background calibration technique for fully dynamic flash ADCs

A fully dynamic flash ADC is attractive for its low-power and low-input capacitance natures. It has minimal static current consumption, and its power and area costs diminish as process advances. However, the comparators thresholds, which are set by the built-in offsets, are sensitive to supply and t...

Full description

Saved in:
Bibliographic Details
Main Authors: Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Calibration
Latches
Modulation
Power dissipation
Resistors
Temperature measurement
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 4
container_issue
container_start_page 1
container_title
container_volume
creator Yun-Shiang Shu
Jui-Yuan Tsai
Ping Chen
Tien-Yu Lo
Pao-Cheng Chiu
description A fully dynamic flash ADC is attractive for its low-power and low-input capacitance natures. It has minimal static current consumption, and its power and area costs diminish as process advances. However, the comparators thresholds, which are set by the built-in offsets, are sensitive to supply and temperature drifts. This threshold variation may result in up to ±20% ADC gain error with ENOB degradation. This paper presents a calibration scheme used to restore the ADC performance without interrupting the normal operation. This technique enables the practical use of fully dynamic flash ADCs and is demonstrated in the quantizer design of a continuous-time ΔΣ modulator. The quantizer accounts for 0.3mW of 3.74mW total power dissipation and relaxes the opamp requirements. The modulator achieves 75.6dB SNDR and 82dB DR over a 10MHz BW, leading to an Walden FoM of 38fJ/conv-step.
doi_str_mv 10.1109/VLDI-DAT.2013.6533857
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6533857</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6533857</ieee_id><sourcerecordid>6533857</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-13d281dd0f7a1f6010161ddced1d2dedf9497f09a6785a39e55478308bff8d363</originalsourceid><addsrcrecordid>eNo1j8tKw0AYRkdEUGueQIR5gdT_z9xXEhIvhYCb6rZMMjN2NE00l0Xe3oJ1dTiL88FHyB3CGhHM_XtVbtIy364zQLaWgjEt1BlJjNLIpWKcM8nPyfW_CH5JknH8BIBjr8DgFXnIaW2br4-hnztHG9vGerBT7Ds6-WbfxZ_Z09APNMxtu1C3dPYQGxpaO-5pXhbjDbkIth19cuKKvD09bouXtHp93hR5lUZUYkqRuUyjcxCUxSABAeVRG-_QZc67YLhRAYyVSgvLjBeCK81A1yFoxyRbkdu_3ei9330P8WCHZXf6zH4BXk5Kuw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A background calibration technique for fully dynamic flash ADCs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Yun-Shiang Shu ; Jui-Yuan Tsai ; Ping Chen ; Tien-Yu Lo ; Pao-Cheng Chiu</creator><creatorcontrib>Yun-Shiang Shu ; Jui-Yuan Tsai ; Ping Chen ; Tien-Yu Lo ; Pao-Cheng Chiu</creatorcontrib><description>A fully dynamic flash ADC is attractive for its low-power and low-input capacitance natures. It has minimal static current consumption, and its power and area costs diminish as process advances. However, the comparators thresholds, which are set by the built-in offsets, are sensitive to supply and temperature drifts. This threshold variation may result in up to ±20% ADC gain error with ENOB degradation. This paper presents a calibration scheme used to restore the ADC performance without interrupting the normal operation. This technique enables the practical use of fully dynamic flash ADCs and is demonstrated in the quantizer design of a continuous-time ΔΣ modulator. The quantizer accounts for 0.3mW of 3.74mW total power dissipation and relaxes the opamp requirements. The modulator achieves 75.6dB SNDR and 82dB DR over a 10MHz BW, leading to an Walden FoM of 38fJ/conv-step.</description><identifier>ISBN: 1467344354</identifier><identifier>ISBN: 9781467344357</identifier><identifier>EISBN: 9781467344364</identifier><identifier>EISBN: 1467344362</identifier><identifier>DOI: 10.1109/VLDI-DAT.2013.6533857</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; Calibration ; Latches ; Modulation ; Power dissipation ; Resistors ; Temperature measurement</subject><ispartof>2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 2013, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6533857$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6533857$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yun-Shiang Shu</creatorcontrib><creatorcontrib>Jui-Yuan Tsai</creatorcontrib><creatorcontrib>Ping Chen</creatorcontrib><creatorcontrib>Tien-Yu Lo</creatorcontrib><creatorcontrib>Pao-Cheng Chiu</creatorcontrib><title>A background calibration technique for fully dynamic flash ADCs</title><title>2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)</title><addtitle>VLDI-DAT</addtitle><description>A fully dynamic flash ADC is attractive for its low-power and low-input capacitance natures. It has minimal static current consumption, and its power and area costs diminish as process advances. However, the comparators thresholds, which are set by the built-in offsets, are sensitive to supply and temperature drifts. This threshold variation may result in up to ±20% ADC gain error with ENOB degradation. This paper presents a calibration scheme used to restore the ADC performance without interrupting the normal operation. This technique enables the practical use of fully dynamic flash ADCs and is demonstrated in the quantizer design of a continuous-time ΔΣ modulator. The quantizer accounts for 0.3mW of 3.74mW total power dissipation and relaxes the opamp requirements. The modulator achieves 75.6dB SNDR and 82dB DR over a 10MHz BW, leading to an Walden FoM of 38fJ/conv-step.</description><subject>Bandwidth</subject><subject>Calibration</subject><subject>Latches</subject><subject>Modulation</subject><subject>Power dissipation</subject><subject>Resistors</subject><subject>Temperature measurement</subject><isbn>1467344354</isbn><isbn>9781467344357</isbn><isbn>9781467344364</isbn><isbn>1467344362</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1j8tKw0AYRkdEUGueQIR5gdT_z9xXEhIvhYCb6rZMMjN2NE00l0Xe3oJ1dTiL88FHyB3CGhHM_XtVbtIy364zQLaWgjEt1BlJjNLIpWKcM8nPyfW_CH5JknH8BIBjr8DgFXnIaW2br4-hnztHG9vGerBT7Ds6-WbfxZ_Z09APNMxtu1C3dPYQGxpaO-5pXhbjDbkIth19cuKKvD09bouXtHp93hR5lUZUYkqRuUyjcxCUxSABAeVRG-_QZc67YLhRAYyVSgvLjBeCK81A1yFoxyRbkdu_3ei9330P8WCHZXf6zH4BXk5Kuw</recordid><startdate>201304</startdate><enddate>201304</enddate><creator>Yun-Shiang Shu</creator><creator>Jui-Yuan Tsai</creator><creator>Ping Chen</creator><creator>Tien-Yu Lo</creator><creator>Pao-Cheng Chiu</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201304</creationdate><title>A background calibration technique for fully dynamic flash ADCs</title><author>Yun-Shiang Shu ; Jui-Yuan Tsai ; Ping Chen ; Tien-Yu Lo ; Pao-Cheng Chiu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-13d281dd0f7a1f6010161ddced1d2dedf9497f09a6785a39e55478308bff8d363</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Bandwidth</topic><topic>Calibration</topic><topic>Latches</topic><topic>Modulation</topic><topic>Power dissipation</topic><topic>Resistors</topic><topic>Temperature measurement</topic><toplevel>online_resources</toplevel><creatorcontrib>Yun-Shiang Shu</creatorcontrib><creatorcontrib>Jui-Yuan Tsai</creatorcontrib><creatorcontrib>Ping Chen</creatorcontrib><creatorcontrib>Tien-Yu Lo</creatorcontrib><creatorcontrib>Pao-Cheng Chiu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yun-Shiang Shu</au><au>Jui-Yuan Tsai</au><au>Ping Chen</au><au>Tien-Yu Lo</au><au>Pao-Cheng Chiu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A background calibration technique for fully dynamic flash ADCs</atitle><btitle>2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)</btitle><stitle>VLDI-DAT</stitle><date>2013-04</date><risdate>2013</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>1467344354</isbn><isbn>9781467344357</isbn><eisbn>9781467344364</eisbn><eisbn>1467344362</eisbn><abstract>A fully dynamic flash ADC is attractive for its low-power and low-input capacitance natures. It has minimal static current consumption, and its power and area costs diminish as process advances. However, the comparators thresholds, which are set by the built-in offsets, are sensitive to supply and temperature drifts. This threshold variation may result in up to ±20% ADC gain error with ENOB degradation. This paper presents a calibration scheme used to restore the ADC performance without interrupting the normal operation. This technique enables the practical use of fully dynamic flash ADCs and is demonstrated in the quantizer design of a continuous-time ΔΣ modulator. The quantizer accounts for 0.3mW of 3.74mW total power dissipation and relaxes the opamp requirements. The modulator achieves 75.6dB SNDR and 82dB DR over a 10MHz BW, leading to an Walden FoM of 38fJ/conv-step.</abstract><pub>IEEE</pub><doi>10.1109/VLDI-DAT.2013.6533857</doi><tpages>4</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 1467344354
ispartof 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 2013, p.1-4
issn
language eng
recordid cdi_ieee_primary_6533857
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Bandwidth
Calibration
Latches
Modulation
Power dissipation
Resistors
Temperature measurement
title A background calibration technique for fully dynamic flash ADCs
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T01%3A08%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20background%20calibration%20technique%20for%20fully%20dynamic%20flash%20ADCs&rft.btitle=2013%20International%20Symposium%20onVLSI%20Design,%20Automation,%20and%20Test%20(VLSI-DAT)&rft.au=Yun-Shiang%20Shu&rft.date=2013-04&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.isbn=1467344354&rft.isbn_list=9781467344357&rft_id=info:doi/10.1109/VLDI-DAT.2013.6533857&rft.eisbn=9781467344364&rft.eisbn_list=1467344362&rft_dat=%3Cieee_6IE%3E6533857%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-13d281dd0f7a1f6010161ddced1d2dedf9497f09a6785a39e55478308bff8d363%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6533857&rfr_iscdi=true