Design of a FinFET based inverter using MTCMOS and SVL leakage reduction technique

Scaling of the Standard single-gate bulk MOSFETs faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage current and enhanced sensitivity to process variations. Double-gate FinFET has better SCEs performance compared to...

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Bibliographic Details
Main Authors: Manorama, Khandelwal, S., Akashe, S.
Format: Conference Proceeding
Language:English
Subjects:
FinFETs
High-performance
Independent gate (IG) mode
Inverters
Leakage currents
Logic gates
Low power (LP) mode
Power demand
Short channel effects (SCEs)
Shorted gate (SG) mode
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Summary:Scaling of the Standard single-gate bulk MOSFETs faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage current and enhanced sensitivity to process variations. Double-gate FinFET has better SCEs performance compared to the conventional CMOS and stimulates technology scaling because of the self-alignment of the two gates. In this paper, we describe different mode of FinFET technology and performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and the total power of the logic circuit, on Cadence Virtuoso tool at 45nm By applying MTCMOS and SVL are effective circuit-level techniques and that provides a high performance and low power design by utilizing both low and high-threshold voltage transistor. The leakage power of the FinFETs based inverter using SVL technique is 50-60% lower than the normal FinFETs based inverter and the total power consumption of FinFETs based inverter using MTCMOS technique is 65-70% lower than the normal FinFETs based inverter.
DOI:10.1109/SCES.2013.6547489